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| Features * 64-megabit (4M x 16) Flash Memory * 2.7V - 3.6V Read/Write * High Performance - Asynchronous Access Time - 70 ns - Page Mode Read Time - 20 ns Sector Erase Architecture - Eight 4K Word Sectors with Individual Write Lockout - One Hundred Twenty-seven 32K Word Main Sectors with Individual Write Lockout Typical Sector Erase Time: 32K Word Sectors - 700 ms; 4K Word Sectors - 200 ms Four Plane Organization, Permitting Concurrent Read in Any of the Three Planes not Being Programmed/Erased - Memory Plane A: 16M Memory Including Eight 4K Word Sectors - Memory Plane B: 16M Memory Consisting of 32K Word Sectors - Memory Plane C: 16M Memory Consisting of 32K Word Sectors - Memory Plane D: 16M Memory Consisting of 32K Word Sectors Suspend/Resume Feature for Erase and Program - Supports Reading and Programming Data from Any Sector by Suspending Erase of a Different Sector - Supports Reading Any Word by Suspending Programming of Any Other Word Low-power Operation - 30 mA Active - 35 A Standby 2.2V I/O Option Reduces Overall System Power VPP Pin for Write Protection and Accelerated Program/Erase Operations Reset Input for Device Initialization CBGA Package Top or Bottom Boot Block Configuration Available 128-bit Protection Register Common Flash Interface (CFI) * * * * 64-megabit (4M x 16) Page Mode 2.7-volt Flash Memory AT49BV6416C AT49BV6416CT * * * * * * * * 1. Description The AT49BV6416C(T) is a 2.7-volt 64-megabit Flash memory. The memory is divided into multiple sectors and planes for erase operations. The device can be read or reprogrammed off a single 2.7V power supply, making it ideally suited for In-System programming. The device can operate in the asynchronous or page read mode. The AT49BV6416C(T) is divided into four memory planes. A read operation can occur in any of the three planes which is not being programmed or erased. This concurrent operation allows improved system performance by not requiring the system to wait for a program or erase operation to complete before a read is performed. To further increase the flexibility of the device, it contains an Erase Suspend and Program Suspend feature. This feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors. There is no reason to suspend the erase or program operation if the data to be read is in another memory plane. The VPP pin provides data protection and faster programming times. When the VPP input is below 0.7V, the program and erase functions are inhibited. When VPP is at 1.65V or above, normal program and erase operations can be performed. With VPP at 10.0V, the program (Dual-word Program command) operation is accelerated. 3465C-FLASH-07/05 2. Pin Configurations Pin Name I/O0 - I/O15 A0 - A21 CE OE WE Reset WP VPP VCCQ Pin Function Data Inputs/Outputs Addresses Chip Enable Output Enable Write Enable Reset Write Protect Write Protection and Power Supply for Accelerated Program/Erase Operations Output Power Supply 2.1 48-ball CBGA - Top View 1 A A13 A11 A10 A12 A8 WE A9 VPP RST A21 WP A18 A20 A19 A17 A6 I/O8 I/O9 A7 A5 A3 CE I/O0 A4 A2 A1 A0 GND OE 2 3 4 5 6 7 8 B A14 C A15 D A16 I/O14 I/O5 I/O11 I/O2 E VCCQ I/O15 I/O6 I/O12 I/O3 F GND I/O7 I/O13 I/O4 VCC I/O10 I/O1 2 AT49BV6416C(T) 3465C-FLASH-07/05 AT49BV6416C(T) 3. Device Operation 3.1 Command Sequences When the device is first powered on, it will be in the read mode. Command sequences are used to place the device in other operating modes such as program and erase. The command sequences are written by applying a low pulse on the WE input with CE low and OE high or by applying a low-going pulse on the CE input with WE low and OE high. The address is latched on the first rising edge of the WE or CE. Valid data is latched on the rising edge of the WE or the CE pulse, whichever occurs first. The addresses used in the command sequences are not affected by entering the command sequences. 3.2 Asynchronous Read The AT49BV6416C(T) is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins are asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. 3.3 Page Read The page read operation of the device is controlled by CE and OE inputs. The page size is four words. The first word access of the page read is the same as the asynchronous read. The first word is read at an asynchronous speed of 70 ns. Once the first word is read, toggling A0 and A1 will result in subsequent reads within the page being output at a speed of 20 ns. See the "Page Read Cycle Waveform" on page 24. 3.4 Reset A Reset input pin is provided to ease some system applications. When Reset is at a logic high level, the device is in its standard operating mode. A low level on the Reset pin halts the present device operation and puts the outputs of the device in a high-impedance state. When a high level is reasserted on the Reset pin, the device returns to read mode. 3.5 Erase Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a logical "1". The entire memory can be erased by using the Chip Erase command or individual planes can be erased by using the Plane Erase command or individual sectors can be erased by using the Sector Erase command. 3.5.1 Chip Erase Chip Erase is a two-bus cycle operation. The automatic erase begins on the rising edge of the last WE pulse. Chip Erase does not alter the data of the protected sectors. The hardware reset during chip erase will stop the erase, but the data will be of an unknown state. 3.5.2 Plane Erase As an alternative to a full Chip Erase, the device is organized into four planes that can be individually erased. The Plane Erase command is a two-bus cycle operation. The plane whose address is valid at the second rising edge of WE will be erased. The Plane Erase command does not alter the data in the protected sectors. 3 3465C-FLASH-07/05 3.5.3 Sector Erase The device is organized into multiple sectors that can be individually erased. The Sector Erase command is a two-bus cycle operation. The sector whose address is valid at the second rising edge of WE will be erased provided the given sector has not been protected. 3.6 Word Programming The device is programmed on a word-by-word basis. Programming is accomplished via the internal device command register and is a two-bus cycle operation. The programming address and data are latched in the second cycle. The device will automatically generate the required internal programming pulses. Please note that a "0" cannot be programmed back to a "1"; only erase operations can convert "0"s to "1"s. 3.7 Flexible Sector Protection The AT49BV6416C(T) offers two sector protection modes, the Softlock and the Hardlock. The Softlock mode is optimized as sector protection for sectors whose content changes frequently. The Hardlock protection mode is recommended for sectors whose content changes infrequently. Once either of these two modes is enabled, the contents of the selected sector is read-only and cannot be erased or programmed. Each sector can be independently programmed for either the Softlock or Hardlock sector protection mode. At power-up and reset, all sectors have their Softlock protection mode enabled. 3.7.1 Softlock And Unlock The Softlock protection mode can be disabled by issuing a two-bus cycle Unlock command to the selected sector. Once a sector is unlocked, its contents can be erased or programmed. To enable the Softlock protection mode, a two-bus cycle Softlock command must be issued to the selected sector. Hardlock And Write Protect (WP) The Hardlock sector protection mode operates in conjunction with the Write Protection (WP) pin. The Hardlock sector protection mode can be enabled by issuing a two-bus cycle Hardlock software command to the selected sector. The state of the Write Protect pin affects whether the Hardlock protection mode can be overridden. * When the WP pin is low and the Hardlock protection mode is enabled, the sector cannot be unlocked and the contents of the sector is read-only. * When the WP pin is high, the Hardlock protection mode is overridden and the sector can be unlocked via the Unlock command. To disable the Hardlock sector protection mode, the chip must be either reset or power cycled. 3.7.2 4 AT49BV6416C(T) 3465C-FLASH-07/05 AT49BV6416C(T) Table 3-1. Hardlock and Softlock Protection Configurations in Conjunction with WP Hardlock 0 0 Softlock 0 1 Erase/ Prog Allowed? Yes No VPP VCC VCC WP 0 0 Comments No sector is locked Sector is Softlocked. The Unlock command can unlock the sector. Hardlock protection mode is enabled. The sector cannot be unlocked. No sector is locked. Sector is Softlocked. The Unlock command can unlock the sector. Hardlock protection mode is overridden and the sector is not locked. Hardlock protection mode is overridden and the sector can be unlocked via the Unlock command. Erase and Program Operations cannot be performed. VCC VCC VCC 0 1 1 1 0 0 1 0 1 No Yes No VCC 1 1 0 Yes VCC 1 1 1 No VIL x x x No Figure 3-1. Sector Locking State Diagram UNLOCKED LOCKED [000] A C B [001] WP = VIL = 0 C [011] Power-Up/Reset Default Hardlocked [110] A C A B B [111] Hardlocked is disabled by WP = VIH WP = VIH = 1 C Power-Up/Reset Default [100] [101] A = Unlock Command B = Softlock Command C = Hardlock Command Note: 1. The notation [X, Y, Z] denotes the locking state of a sector. The current locking state of a sector is defined by the state of WP and the two bits of the sector-lock status D[1:0]. 5 3465C-FLASH-07/05 3.7.3 Sector Protection Detection A software method is available to determine if the sector protection Softlock or Hardlock features are enabled. When the device is in the software product identification mode a read from the I/O0 and I/O1 at address location 00002H within a sector will show if the sector is unlocked, softlocked, or hardlocked. Table 3-2. I/O1 0 0 1 1 Sector Protection Status I/O0 0 1 0 1 Sector Protection Status Sector Not Locked Softlock Enabled Hardlock Enabled Both Hardlock and Softlock Enabled 3.8 Read Status Register The status register indicates the status of device operations and the success/failure of that operation. The Read Status Register command causes subsequent reads to output data from the status register until another command is issued. To return to reading from the memory, issue a Read command. The status register bits are output on I/O7 - I/O0. The upper byte, I/O15 - I/O8, outputs 00H when a Read Status Register command is issued. The contents of the status register [SR7:SR0] are latched on the falling edge of OE or CE (whichever occurs last), which prevents possible bus errors that might occur if status register contents change while being read. CE or OE must be toggled with each subsequent status read, or the status register will not indicate completion of a Program or Erase operation. When the Write State Machine (WSM) is active, SR7 will indicate the status of the WSM; the remaining bits in the status register indicate whether the WSM was successful in performing the preferred operation (see Table 3-3 on page 7). 6 AT49BV6416C(T) 3465C-FLASH-07/05 AT49BV6416C(T) Table 3-3. WSMS 7 Status Register Bit Definition ESS 6 ES 5 PRS 4 VPPS 3 PSS 2 Notes SLS 1 PLS 0 SR7 WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR6 = ERASE SUSPEND STATUS (ESS) 1 = Erase Suspended 0 = Erase In Progress/Completed SR5 = ERASE STATUS (ES) 1 = Error in Sector Erase 0 = Successful Sector Erase SR4 = PROGRAM STATUS (PRS) 1 = Error in Programming 0 = Successful Programming SR3 = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK SR2 = PROGRAM SUSPEND STATUS (PSS) 1 = Program Suspended 0 = Program in Progress/Completed SR1 = SECTOR LOCK STATUS 1 = Prog/Erase attempted on a locked sector; Operation aborted. 0 = No operation to locked sectors SR0 = Plane Status (PLS) Note: Check Write State Machine bit first to determine Word Program or Sector Erase completion, before checking program or erase status bits. When Erase Suspend is issued, WSM halts execution and sets both WSMS and ESS bits to "1" - ESS bit remains set to "1" until an Erase Resume command is issued. When this bit is set to "1", WSM has applied the max number of erase pulses to the sector and is still unable to verify successful sector erasure. When this bit is set to "1", WSM has attempted but failed to program a word The VPP status bit does not provide continuous indication of VPP level. The WSM interrogates VPP level only after the Program or Erase command sequences have been entered and informs the system if VPP has not been switched on. The VPP is also checked before the operation is verified by the WSM. When Program Suspend is issued, WSM halts execution and sets both WSMS and PSS bits to "1". PSS bit remains set to "1" until a Program Resume command is issued. If a Program or Erase operation is attempted to one of the locked sectors, this bit is set by the WSM. The operation specified is aborted and the device is returned to read status mode. Indicates program or erase status of the addressed plane. 1. A Command Sequence Error is indicated when SR1, SR3, SR4 and SR5 are set. Table 3-4. WSMS (SR7) 0 0 1 Status Register Device WSMS and Write Status Definition PLS (SR0) 0 1 x Description The addressed plane is performing a program/erase operation. A plane other than the one currently addressed is performing a program/erase operation. No program/erase operation is in progress in any plane. Erase and Program suspend bits (SR6, SR2) indicate whether other planes are suspended. 7 3465C-FLASH-07/05 3.9 Erase Suspend/Erase Resume The Erase Suspend command allows the system to interrupt a sector erase or plane erase operation. The erase suspend command does not work with the Chip Erase feature. Using the erase suspend command to suspend a sector erase operation, the system can program or read data from a different sector within the same plane. Since this device is organized into four planes, there is no need to use the erase suspend feature while erasing a sector when you want to read data from a sector in another plane. After the Erase Suspend command is given, the device requires a maximum time of 15 s to suspend the erase operation. After the erase operation has been suspended, the plane that contains the suspended sector enters the erase-suspend-read mode. The system can then read data or program data to any other sector within the device. An address is not required during the Erase Suspend command. During a sector erase suspend, another sector cannot be erased. To resume the sector erase operation, the system must write the Erase Resume command. The Erase Resume command is a one-bus cycle command, which does require the plane address. Read, Read Status Register, Product ID Entry, Clear Status Register, Program, Program Suspend, Erase Resume, Sector Softlock/Hardlock, Sector Unlock are valid commands during an erase suspend. 3.10 Program Suspend/Program Resume The Program Suspend command allows the system to interrupt a programming operation and then read data from a different word within the memory. After the Program Suspend command is given, the device requires a maximum of 10 s to suspend the programming operation. After the programming operation has been suspended, the system can then read from any other word within the device. An address is not required during the program suspend operation. To resume the programming operation, the system must write the Program Resume command. The program suspend and resume are one-bus cycle commands. The command sequence for the erase suspend and program suspend are the same, and the command sequence for the erase resume and program resume are the same. Read, Read Status Register, Product ID Entry, Program Resume are valid commands during a Program Suspend. 3.11 128-bit Protection Register The AT49BV6416C(T) contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are designated as block A and block B. The data in block A is non-changeable and is programmed at the factory with a unique number. The data in block B is programmed by the user and can be locked out such that data in the block cannot be reprogrammed. To program block B in the protection register, the two-bus cycle Program Protection Register command must be used as shown in the "Command Definition Table" on page 15. To lock out block B, the two-bus cycle lock protection register command must be used as shown in the Command Definition table. Data bit D1 must be zero during the second bus cycle. All other data bits during the second bus cycle are don't cares. To determine whether block B is locked out, the Status of Sector B Protection command is given. If data bit D1 is zero, block B is locked. If data bit D1 is one, block B can be reprogrammed. Please see the "Protection Register Addressing Table" on page 16 for the address locations in the protection register. To read the protection register, the Product ID Entry command is given followed by a normal read operation from an address within the protection register. After determining whether block B is protected or not or reading the protection register, the Read command must be given to return to the read mode. 8 AT49BV6416C(T) 3465C-FLASH-07/05 AT49BV6416C(T) 3.12 Common Flash Interface (CFI) CFI is a published, standardized data structure that may be read from a flash device. CFI allows system software to query the installed device to determine the configurations, various electrical and timing parameters, and functions supported by the device. CFI is used to allow the system to learn how to interface to the flash device most optimally. The two primary benefits of using CFI are ease of upgrading and second source availability. The command to enter the CFI Query mode is a one-bus cycle command which requires writing data 98h to any address. The CFI Query command can be written when the device is ready to read data or can also be written when the part is in the product ID mode. Once in the CFI Query mode, the system can read CFI data at the addresses given in the "Common Flash Interface Definition Table" on page 27. To return to the read mode, the read command should be issued. 3.13 Hardware Data Protection Hardware features protect against inadvertent programs to the AT49BV6416C(T) in the following ways: (a) VCC sense: if VCC is below 1.8V (typical), the device is reset and the program and erase functions are inhibited. (b) VCC power-on delay: once VCC has reached the VCC sense level, the device will automatically time-out 10 ms (typical) before programming. (c) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. (e) VPP is less than VILPP. 3.14 Input Levels While operating with a 2.7V to 3.6V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can be driven from 0 to VCCQ + 0.6V. 3.15 Output Levels For the AT49BV6416C(T), output high levels are equal to VCCQ - 0.1V (not VCC). For 2.7V to 3.6V output levels, VCCQ must be tied to VCC. 9 3465C-FLASH-07/05 3.16 Word Program Flowchart Start 3.17 Word Program Procedure Command Program Setup Data Comments Data = 40 Addr = Location to program Data = Data to program Addr = Location to program Status register data: Toggle CE or OE to update status register Check SR7 1 = WSM Ready 0 = WSM Busy Bus Operation Write Write 40, Word Address (Setup) Write Write Data, Word Address Read Status Register No (Confirm) Read Program Suspend Loop None Idle Yes None SR7 = 1 0 Suspend? Full Status Check (If Desired) Repeat for subsequent Word Program operations. Full status register check can be done after each program, or after a sequence of program operations. Write FF after the last operation to set to the Read state. Program Complete 3.18 Full Status Check Flowchart Read Status Register 3.19 Full Status Check Procedure Command None None Comments Check SR3: 1 = VPP Error Check SR4: 1 = Data Program Error Check SR1: 1 = Sector locked; operation aborted Bus Operation Idle SR3 = 0 1 VP P Range Error Idle SR4 = 0 1 Program Error Idle None SR1 = 0 1 Device Protect Error SR3 MUST be cleared before the Write State Machine allows further program attempts. If an error is detected, clear the status register before continuing operations - only the Clear Status Register command clears the status register error bits. Program Successful 10 AT49BV6416C(T) 3465C-FLASH-07/05 AT49BV6416C(T) 3.20 Program Suspend/Resume Flowchart Start 3.21 Program Suspend/Resume Procedure Command Program Suspend Read Status Comments Data = B0 Addr = Sector address to Suspend (SA) Data = 70 Addr = Any address within the Same Plane Status register data: Toggle CE or OE to update status register Addr = Any address Check SR7 1 = WSM Ready 0 = WSM Busy Check SR2 1 = Program suspended 0 = Program completed Data = FF Addr = Any address within the Suspended Plane Read data from any sector in the memory other than the one being programmed Data = D0 Addr = Any address Bus Operation (Program Suspend) Write B0 Any Address Write Write 70 Any Address (Read Status) within the Same Plane Read Status Register Write Read SR7 = 1 0 0 None SR2 = 1 Program Completed Idle None Write FF Suspend Plane (Read Array) Idle None Read Data Write FF (Read Array) Write Read Array Done Reading Yes No Read Data Read (Program Resume) None Program Resume Write D0 Any Address Write Program Resumed If the Suspend Plane was placed in Read mode: Read Status Return Plane to Status mode: Data = 70 Addr = Any address within the Same Plane Write 70H Any Address within the Same Plane (Read Status) Write 11 3465C-FLASH-07/05 3.22 Sector Erase Flowchart Start 3.23 Sector Erase Procedure Command Sector Erase Setup Erase Confirm None Comments Data = 20 Addr = Sector to be erased (SA) Data = D0 Addr = Sector to be erased (SA) Status register data: Toggle CE or OE to update status register data Check SR7 1 = WSMS Ready 0 = WSMS Busy Bus Operation (Sector Erase) Write 20, Sector Address Write Write D0, (Erase Confirm) Sector Address Read Status Register No Write Suspend Erase Loop Read SR7 = 1 0 Suspend Erase Yes Idle None Full Erase Status Check (If Desired) Sector Erase Complete Repeat for subsequent sector erasures. Full status register check can be done after each sector erase, or after a sequence of sector erasures. Write FF after the last operation to enter read mode. 3.24 Full Erase Status Check Flowchart Read Status Register 1 3.25 Full Erase Status Check Procedure Command None Comments Check SR3: 1 = VPP Range Error Check SR4, SR5: Both 1 = Command Sequence Error Check SR5: 1 = Sector Erase Error Check SR1: 1 = Attempted erase of locked sector; erase aborted. Bus Operation VP P Range Error Command Sequence Error SR3 = 0 SR4, SR5= Idle 1,1 Idle None 0 SR5 = 0 1 Sector Erase Error Idle None SR1 = 0 1 Sector Locked Error Idle None Sector Erase Successful SR1, SR3 must be cleared before the Write State Machine allows further erase attempts. Only the Clear Status Register command clears SR1, SR3, SR4, SR5. If an error is detected, clear the status register before attempting an erase retry or other error recovery. 12 AT49BV6416C(T) 3465C-FLASH-07/05 AT49BV6416C(T) 3.26 Erase Suspend/Resume Flowchart Start 3.27 Erase Suspend/Resume Procedure Command Erase Suspend Read Status Comments Data = B0 Addr = Any address within the Same Plane Data = 70 Addr = Any address Status register data: Toggle CE or OE to update status register Addr = Any address within the Same Plane Check SR7 1 = WSM Ready 0 = WSM Busy Check SR6 1 = Erase suspended 0 = Erase completed Data = FF or 40 Addr = Any address Read or program data from/to sector other than the one being erased Data = D0 Addr = Any address Bus Operation (Erase Suspend) Write B0, Any Address Write Write 70, Any Address Read Status Register (Read Status) Write SR7 = 1 0 Read None SR6 = 1 0 Erase Completed Idle None Read or Program? Read No Program Loop Idle None Done? Yes (Erase Resume) Write Read or Write Write Read or Program None Program Resume Write D0, Any Address Erase Resumed Write FF (Read Array) Read Array Data Write 70H Any Address within the Same Plane (Read Status) If the Suspended Plane was placed in Read mode or a Program loop: Read Status Return Plane to Status mode: Data = 70 Addr = Any address within the Same Plane Write 13 3465C-FLASH-07/05 3.28 Protection Register Programming Flowchart Start 3.29 Protection Register Programming Procedure Command Program PR Setup Protection Program None Comments Data = C0 Addr = First Location to Program Data = Data to Program Addr = Location to Program Status register data: Toggle CE or OE to update status register data Check SR7 1 = WSMS Ready 0 = WSMS Busy Bus Operation (Program Setup) Write C0, PR Address Write Write Write PR Address & Data (Confirm Data) Read Status Register Read SR7 = 1 0 Idle None Full Status Check (If Desired) Program Complete Program Protection Register operation addresses must be within the protection register address space. Addresses outside this space will return an error. Repeat for subsequent programming operations. Full status register check can be done after each program, or after a sequence of program operations. Write FF after the last operation to return to the Read mode. 3.30 Full Status Check Flowchart Read Status Register Data 3.31 Full Status Check Procedure Command None None Comments Check SR1, SR3, SR4: 0,1,1 = VPP Range Error Check SR1, SR3, SR4: 0,0,1 = Programming Error Check SR1, SR3, SR4: 1, 0,1 = Sector locked; operation aborted Bus Operation 1, 1 SR3, SR4 = 0 Idle VP P Range Error Idle 0, 1 SR1, SR4 = Program Error Idle 0 None SR1, SR4 = 0 1, 1 Register Locked; Program Aborted Program Successful SR3 must be cleared before the Write State Machine allows further program attempts. Only the Clear Status Register command clears SR1, SR3, SR4. If an error is detected, clear the status register before attempting a program retry or other error recovery. 14 AT49BV6416C(T) 3465C-FLASH-07/05 AT49BV6416C(T) 4. Command Definition Table Bus Cycles 1 2 2 2 2 (5) 1st Bus Cycle Addr PA(2) xx xx SA(3) Addr (4) 2nd Bus Cycle Data FF 21 22 20 40/10 E0 B0 D0 90 60 60 60 70 50 SA(3) SA (3) 3rd Bus Cycle Data Addr Data Command Sequence Read Chip Erase Plane Erase Sector Erase Word Program Dual Word Program Addr Addr Addr SA(3) Addr (4) D0 D0 D0 DIN DIN0 Addr1 DIN1 3 1 1 1 2 2 2 2 1 2 2 2 1 Addr0 xx PA(2) PA(2) SA SA (3) (3) Addr0 Erase/Program Suspend Erase/Program Resume Product ID Entry(6)(7) Sector Softlock Sector Hardlock Sector Unlock Read Status Register Clear Status Register Program Protection Register- Block B Lock Protection Register - Sector B Status of Sector B Protection CFI Query Notes: 01 2F D0 DOUT(8) SA(3) PA (2) SA(3) PA (7) xx xxxx (10) 8x (9) C0 C0 90 98 xxxx(10)8x(9) xxxx80(10) xxxx80 (10) DIN FFFD DOUT(11) xxxx80(10) xxxx80 xx (10) 1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). I/O15 - I/O8 are don't care. The ADDRESS FORMAT shown for each bus cycle is as follows: A7 - A0 (Hex). Address A21 through A8 are don't care. 2. PA is the plane address (A21 - A20). Any address within a plane can be used. 3. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 17 - 20 for details). 4. The first bus cycle address should be the same as the word address to be programmed. 5. This fast programming option enables the user to program two words in parallel only when VPP = 10V. The addresses, Addr0 and Addr1, of the two words, DIN0 and DIN1, must only differ in address A0. This command should be used during manufacturing purposes only. 6. During the second bus cycle, the manufacturer code is read from address PA+00000H, the device code is read from address PA+00001H, and the data in the protection register is read from addresses 000081H - 000088H. 7. The plane address should be the same during the first and second bus cycle. 8. The status register bits are output on I/O7 - I/O0. 9. Any address within the user programmable protection register region. Please see "Protection Register Addressing Table" on page 16 10. For the AT49BV6416C, xxxx = 0000H. For the AT49BV6416CT, xxxx = 3F80H. 11. If data bit D1 is "0", sector B is locked. If data bit D1 is "1", sector B can be reprogrammed. 15 3465C-FLASH-07/05 5. Absolute Maximum Ratings* Temperature under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages Except VPP (Including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V VPP Input Voltage with Respect to Ground ............................................ 0V to 10V All Output Voltages with Respect to Ground ...........................-0.6V to VCCQ + 0.6V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 6. Protection Register Addressing Table Word 0 1 2 3 4 5 6 7 Notes: Use Factory Factory Factory Factory User User User User Block A A A A B B B B A7 1 1 1 1 1 1 1 1 A6 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 1 A2 0 0 0 1 1 1 1 0 A1 0 1 1 0 0 1 1 0 A0 1 0 1 0 1 0 1 0 1. For the AT49BV6416C, all address lines not specified in the above table, A21 - A8, must be 0 when accessing the Protection Register. 2. For the AT49BV6416CT, all address lines not specified in the table, A21 - A8, must be 3F80H when accessing the Protection Register. 16 AT49BV6416C(T) 3465C-FLASH-07/05 AT49BV6416C(T) 7. Memory Organization - AT49BV6416C x16 Plane A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 Size (Words) 4K 4K 4K 4K 4K 4K 4K 4K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 00000 - 00FFF 01000 - 01FFF 02000 - 02FFF 03000 - 03FFF 04000 - 04FFF 05000 - 05FFF 06000 - 06FFF 07000 - 07FFF 08000 - 0FFFF 10000 - 17FFF 18000 - 1FFFF 20000 - 27FFF 28000 - 2FFFF 30000 - 37FFF 38000 - 3FFFF 40000 - 47FFF 48000 - 4FFFF 50000 - 57FFF 58000 - 5FFFF 60000 - 67FFF 68000 - 6FFFF 70000 - 77FFF 78000 - 7FFFF 80000 - 87FFF 88000 - 8FFFF 90000 - 97FFF 98000 - 9FFFF A0000 - A7FFF A8000 - AFFFF B0000 - B7FFF B8000 - BFFFF C0000 - C7FFF C8000 - CFFFF D0000 - D7FFF D8000 - DFFFF E0000 - E7FFF Plane A A A B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B C Sector SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 7. Memory Organization - AT49BV6416C (Continued) x16 Address Range (A21 - A0) E8000 - EFFFF F0000 - F7FFF F8000 - FFFFF 100000 - 107FFF 108000 - 10FFFF 110000 - 117FFF 118000 - 11FFFF 120000 - 127FFF 128000 - 12FFFF 130000 - 137FFF 138000 - 13FFFF 140000 - 147FFF 148000 - 14FFFF 150000 - 157FFF 158000 - 15FFFF 160000 - 167FFF 168000 - 16FFFF 170000 - 177FFF 178000 - 17FFFF 180000 - 187FFF 188000 - 18FFFF 190000 - 197FFF 198000 - 19FFFF 1A0000 - 1A7FFF 1A8000 - 1AFFFF 1B0000 - 1B7FFF 1B8000 - 1BFFFF 1C0000 - 1C7FFF 1C8000 - 1CFFFF 1D0000 - 1D7FFF 1D8000 - 1DFFFF 1E0000 - 1E7FFF 1E8000 - 1EFFFF 1F0000 - 1F7FFF 1F8000 - 1FFFFF 200000 - 207FFF 17 3465C-FLASH-07/05 7. Memory Organization - AT49BV6416C (Continued) x16 Plane C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C D D D D D Sector SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 208000 - 20FFFF 210000 - 217FFF 218000 - 21FFFF 220000 - 227FFF 228000 - 22FFFF 230000 - 237FFF 238000 - 23FFFF 240000 - 247FFF 248000 - 24FFFF 250000 - 257FFF 258000 - 25FFFF 260000 - 267FFF 268000 - 26FFFF 270000 - 277FFF 278000 - 27FFFF 280000 - 287FFF 288000 - 28FFFF 290000 - 297FFF 298000 - 29FFFF 2A0000 - 2A7FFF 2A8000 - 2AFFFF 2B0000 - 2B7FFF 2B8000 - 2BFFFF 2C0000 - 2C7FFF 2C8000 - 2CFFFF 2D0000 - 2D7FFF 2D8000 - 2DFFFF 2E0000 - 2E7FFF 2E8000 - 2EFFFF 2F0000 - 2F7FFF 2F8000 - 2FFFFF 300000 - 307FFF 308000 - 30FFFF 310000 - 317FFF 318000 - 31FFFF 320000 - 327FFF 7. Memory Organization - AT49BV6416C (Continued) x16 Plane D D D D D D D D D D D D D D D D D D D D D D D D D D D Sector SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 328000 - 32FFFF 330000 - 337FFF 338000 - 33FFFF 340000 - 347FFF 348000 - 34FFFF 350000 - 357FFF 358000 - 35FFFF 360000 - 367FFF 368000 - 36FFFF 370000 - 377FFF 378000 - 37FFFF 380000 - 387FFF 388000 - 38FFFF 390000 - 397FFF 398000 - 39FFFF 3A0000 - 3A7FFF 3A8000 - 3AFFFF 3B0000 - 3B7FFF 3B8000 - 3BFFFF 3C0000 - 3C7FFF 3C8000 - 3CFFFF 3D0000 - 3D7FFF 3D8000 - 3DFFFF 3E0000 - 3E7FFF 3E8000 - 3EFFFF 3F0000 - 3F7FFF 3F8000 - 3FFFFF 18 AT49BV6416C(T) 3465C-FLASH-07/05 AT49BV6416C(T) 8. Memory Organization - AT49BV6416CT x16 Plane D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D C C C C Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 00000 - 07FFF 08000 - 0FFFF 10000 - 17FFF 18000 - 1FFFF 20000 - 27FFF 28000 - 2FFFF 30000 - 37FFF 38000 - 3FFFF 40000 - 47FFF 48000 - 4FFFF 50000 - 57FFF 58000 - 5FFFF 60000 - 67FFF 68000 - 6FFFF 70000 - 77FFF 78000 - 7FFFF 80000 - 87FFF 88000 - 8FFFF 90000 - 97FFF 98000 - 9FFFF A0000 - A7FFF A8000 - AFFFF B0000 - B7FFF B8000 - BFFFF C0000 - C7FFF C8000 - CFFFF D0000 - D7FFF D8000 - DFFFF E0000 - E7FFF E8000 - EFFFF F0000 - F7FFF F8000 - FFFFF 100000 - 107FFF 108000 - 10FFFF 110000 - 117FFF 118000 - 11FFFF Plane C C C C C C C C C C C C C C C C C C C C C C C C C C C C B B B B B B B B Sector SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 8. Memory Organization - AT49BV6416CT (Continued) x16 Address Range (A21 - A0) 120000 - 127FFF 128000 - 12FFFF 130000 - 137FFF 138000 - 13FFFF 140000 - 147FFF 148000 - 14FFFF 150000 - 157FFF 158000 - 15FFFF 160000 - 167FFF 168000 - 16FFFF 170000 - 177FFF 178000 - 17FFFF 180000 - 187FFF 188000 - 18FFFF 190000 - 197FFF 198000 - 19FFFF 1A0000 - 1A7FFF 1A8000 - 1AFFFF 1B0000 - 1B7FFF 1B8000 - 1BFFFF 1C0000 - 1C7FFF 1C8000 - 1CFFFF 1D0000 - 1D7FFF 1D8000 - 1DFFFF 1E0000 - 1E7FFF 1E8000 - 1EFFFF 1F0000 - 1F7FFF 1F8000 - 1FFFFF 200000 - 207FFF 208000 - 20FFFF 210000 - 217FFF 218000 - 21FFFF 220000 - 227FFF 228000 - 22FFFF 230000 - 237FFF 238000 - 23FFFF 19 3465C-FLASH-07/05 8. Memory Organization - AT49BV6416CT (Continued) x16 Plane B B B B B B B B B B B B B B B B B B B B B B B B A A A A A A A A A A A A Sector SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K Address Range (A21 - A0) 240000 - 247FFF 248000 - 24FFFF 250000 - 257FFF 258000 - 25FFFF 260000 - 267FFF 268000 - 26FFFF 270000 - 277FFF 278000 - 27FFFF 280000 - 287FFF 288000 - 28FFFF 290000 - 297FFF 298000 -29FFFF 2A0000 - 2A7FFF 2A8000 - 2AFFFF 2B0000 - 2B7FFF 2B8000 - 2BFFFF 2C0000 - 2C7FFF 2C8000 - 2CFFFF 2D0000 - 2D7FFF 2D8000 - 2DFFFF 2E0000 - 2E7FFF 2E8000 - 2EFFFF 2F0000 - 2F7FFF 2F8000 - 2FFFFF 300000 - 307FFF 308000 - 30FFFF 310000 - 317FFF 318000 - 31FFFF 320000 - 327FFF 328000 - 32FFFF 330000 - 337FFF 338000 - 33FFFF 340000 - 347FFF 348000 - 34FFFF 350000 - 357FFF 358000 - 35FFFF 8. Memory Organization - AT49BV6416CT (Continued) x16 Plane A A A A A A A A A A A A A A A A A A A A A A A A A A A Sector SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 Size (Words) 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 32K 4K 4K 4K 4K 4K 4K 4K 4K Address Range (A21 - A0) 360000 - 367FFF 368000 - 36FFFF 370000 - 377FFF 378000 - 37FFFF 380000 - 387FFF 388000 - 38FFFF 390000 - 397FFF 398000 - 39FFFF 3A0000 - 3A7FFF 3A8000 - 3AFFFF 3B0000 - 3B7FFF 3B8000 - 3BFFFF 3C0000 - 3C7FFF 3C8000 - 3CFFFF 3D0000 - 3D7FFF 3D8000 - 3DFFFF 3E0000 - 3E7FFF 3E8000 - 3EFFFF 3F0000 - 3F7FFF 3F8000 - 3F8FFF 3F9000 - 3F9FFF 3FA000 - 3FAFFF 3FB000 - 3FBFFF 3FC000 - 3FCFFF 3FD000 - 3FDFFF 3FE000 - 3FEFFF 3FF000 - 3FFFFF 20 AT49BV6416C(T) 3465C-FLASH-07/05 AT49BV6416C(T) 9. DC and AC Operating Range AT49BV6416C(T)-70 Operating Temperature (Case) VCC Power Supply Industrial -40C - 85C 2.7V - 3.6V 10. Operating Modes Mode Read Program/Erase (3) CE VIL VIL VIH X OE VIL VIH X(1) X VIL X VIH X WE VIH VIL X VIH X X X X Reset VIH VIH VIH VIH VIH X VIH VIL VPP(4) X VIHPP(5) X X X VILPP(6) X X Ai Ai Ai X I/O DOUT DIN High Z Standby/Program Inhibit Program Inhibit X X Output Disable Reset Product Identification Software Notes: X X High Z X High Z VIH A0 = VIL, A1 - A21 = VIL A0 = VIH, A1 - A21 = VIL Manufacturer Code(3) Device Code(3) 1. X can be VIL or VIH. 2. Refer to AC programming waveforms. 3. Manufacturer Code: 001FH; Device Code: 00C5H - AT49BV6416C; 00DFH - AT49BV6416CT 4. The VPP pin can be tied to VCC. For faster program/erase operations, VPP can be set to 9.5V 0.5V. 5. VIHPP (min) = 1.65V. 6. VILPP (max) = 0.7V. 21 3465C-FLASH-07/05 11. DC Characteristics Symbol ILI ILO ISB1 ICC(1) ICCRE ICCRW VIL VIH VOL VOH Note: Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Active Current VCC Read While Erase Current VCC Read While Write Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 1. In the erase mode, ICC is 35 mA. IOL = 2.1 mA IOH = -100 A; VCCQ = 2.2V - 3.6V VCCQ - 0.1 VCCQ - 0.6 0.45 Condition VIN = 0V to VCC VI/O = 0V to VCC CE = VCCQ - 0.3V to VCC f = 5 MHz; IOUT = 0 mA f = 5 MHz; IOUT = 0 mA f = 5 MHz; IOUT = 0 mA Min Max 1 1 35 30 60 60 0.6 Units A A A mA mA mA V V V V 12. Input Test Waveforms and Measurement Level 2.0V AC DRIVING LEVELS 0.6V 1.5V AC MEASUREMENT LEVEL tR, tF < 5 ns 13. Output Test Load VCCQ 1.8K OUTPUT PIN 1.3K 30 pF 14. Pin Capacitance f = 1 MHz, T = 25C(1) Typ CIN COUT Note: 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V 1. This parameter is characterized and is not 100% tested. 22 AT49BV6416C(T) 3465C-FLASH-07/05 AT49BV6416C(T) 15. AC Asynchronous Read Timing Characteristics Symbol tRC tACC tCE tOE tDF tOH tRO Parameter Read Cycle Time Access, Address to Data Valid Access, CE to Data Valid OE to Data Valid CE, OE High to Data Float Output Hold from OE, CE or Address, whichever Occurs First Reset to Output Delay 0 150 Min 70 70 70 20 25 Max Units ns ns ns ns ns ns ns 16. Asynchronous Read Cycle Waveform(1)(2)(3) tRC A0 - A21 ADDRESS VALID CE tCE OE tOE tDF tACC tRO HIGH Z OUTPUT VALID tOH RESET I/O0 - I/O15 Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF). 23 3465C-FLASH-07/05 17. AC Asynchronous Read Timing Characteristics Symbol tACC tCE tOE tDF tRO tPAA Parameter Access, Address to Data Valid Access, CE to Data Valid OE to Data Valid CE, OE High to Data Float Reset to Output Delay Page Address Access Time Min Max 70 70 20 25 150 20 Units ns ns ns ns ns ns 18. Page Read Cycle Waveform tCE CE tDF I/O0-I/O15 tACC A2 -A21 tPAA tACC A0 -A1 DATA VALID tDF OE tRO RESET tOE 24 AT49BV6416C(T) 3465C-FLASH-07/05 AT49BV6416C(T) 19. AC Word Load Characteristics Symbol tAS tAH tDS tDH tWP tWPH Parameter Address Setup Time to WE and CE High Address Hold Time Data Setup Time Data Hold Time CE or WE Low Pulse Width CE or WE High Pulse Width Min 50 0 50 0 35 25 Max Units ns ns ns ns ns ns 20. AC Word Load Waveforms 20.1 WE Controlled CE I/O0 - I/O15 DATA VALID A0 - A21 WE 20.2 CE Controlled WE I/O0 - I/O15 DATA VALID A0 - A21 CE 25 3465C-FLASH-07/05 21. Program Cycle Characteristics Symbol tBP tSEC1 tSEC2 tES tPS tERES Parameter Word Programming Time Sector Erase Cycle Time (4K word sectors) Sector Erase Cycle Time (32K word sectors) Erase Suspend Time Program Suspend Time Delay between Erase Resume and Erase Suspend 500 Min Typ 15 200 700 15 10 Max Units s ms ms s s s 22. Program Cycle Waveforms PROGRAM CYCLE OE (2) CE tWP tBP WE tAS tWPH tDH tAH (1) A0 - A21 XX ADDRESS tWC tDS INPUT DATA I/O0 - I/O15 Note 3 23. Sector, Plane or Chip Erase Cycle Waveforms OE (2) CE tWP WE tAS tWPH tDH tAH (1) A0 - A21 XX Note 4 tWC tDS tSEC1/2 D0 I/O0 - I/O15 Note 5 WORD 0 WORD 1 Notes: 1. Any address can be used to load data. 2. OE must be high only when WE and CE are both low. 3. The data can be 40H or 10H. 4. For chip erase, any address can be used. For plane erase or sector erase, the address depends on what plane or sector is to be erased. 5. For chip erase, the data should be 21H, for plane erase, the data should be 22H, and for sector erase, the data should be 20H. 26 AT49BV6416C(T) 3465C-FLASH-07/05 AT49BV6416C(T) 24. Common Flash Interface Definition Table Address 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h AT49BV6416CT 0051h 0052h 0059h 0003h 0000h 0041h 0000h 0000h 0000h 0000h 0000h 0027h 0036h 0009h 000Ah 0004h 0000h 0009h 0010h 0004h 0000h 0003h 0003h 0017h 0001h 0000h 0000h 0000h 0002h 007Eh 0000h 0000h 0001h 0007h 0000h 0020h 0000h AT49BV6416C 0051h 0052h 0059h 0003h 0000h 0041h 0000h 0000h 0000h 0000h 0000h 0027h 0036h 0009h 000Ah 0004h 0000h 0009h 0010h 0004h 0000h 0003h 0003h 0017h 0001h 0000h 0000h 0000h 0002h 0007h 0000h 0020h 0000h 007Eh 0000h 0000h 0001h Typ block erase - 500 ms Typ chip erase - 64,300 ms Max word write/typ time n/a Max block erase/typ block erase Max chip erase/ typ chip erase Device size x16 device x16 device Multiple byte write not supported Multiple byte write not supported 2 regions, x = 2 64K bytes, Y = 126 (Top); 8K bytes, Y = 7 (Bottom) 64K bytes, Y = 126 (Top); 8K bytes, Y = 7 (Bottom) 64K bytes, Z = 256 (Top); 8K bytes, Z = 32 (Bottom) 64K bytes, Z = 256 (Top); 8K bytes, Z = 32 (Bottom) 8K bytes, Y = 7 (Top); 64K bytes, Y = 126 (Bottom) 8K bytes, Y = 7 (Top); 64K bytes, Y = 126 (Bottom) 8K bytes, Z = 32 (Top);64K bytes, Z = 256 (Bottom) 8K bytes, Z = 32 (Top);64K bytes, Z = 256 (Bottom) VCC min write/erase VCC max write/erase VPP min voltage VPP max voltage Typ word write - 15 s Comments "Q" "R" "Y" 27 3465C-FLASH-07/05 24. Common Flash Interface Definition Table Address AT49BV6416CT AT49BV6416C Comments VENDOR SPECIFIC EXTENDED QUERY 41h 42h 43h 44h 45h 0050h 0052h 0049h 0031h 0030h 0050h 0052h 0049h 0031h 0030h "P" "R" "I" Major version number, ASCII Minor version number, ASCII Bit 0 - chip erase supported, 0 - no, 1 - yes Bit 1 - erase suspend supported, 0 - no, 1 - yes Bit 2 - program suspend supported, 0 - no, 1 - yes Bit 3 - simultaneous operations supported, 0 - no, 1 - yes Bit 4 - burst mode read supported, 0 - no, 1 - yes Bit 5 - page mode read supported, 0 - no, 1 - yes Bit 6 - queued erase supported, 0 - no, 1 - yes Bit 7 - protection bits supported, 0 - no, 1 - yes Bit 0 - top ("0") or bottom ("1") boot block device Undefined bits are "0" Bit 0 - 4 word linear burst with wrap around, 0 - no, 1 - yes Bit 1 - 8 word linear burst with wrap around, 0 - no, 1 - yes Bit 2 - 16 word linear burst with wrap around, 0 - no, 1 - yes Bit 3 - continuous burst, 0 - no, 1 - yes Undefined bits are "0" Bit 0 - 4 word page, 0 - no, 1 - yes Bit 1 - 8 word page, 0 - no, 1 - yes Undefined bits are "0" Location of protection register lock byte, the section's first byte # of bytes in the factory prog section of prot register - 2*n # of bytes in the user prog section of prot register - 2*n 46h 00AFh 00AFh 47h 0000h 0001h 48h 0000h 0000h 49h 4Ah 4Bh 4Ch 0001h 0080h 0003h 0003h 0001h 0080h 0003h 0003h 28 AT49BV6416C(T) 3465C-FLASH-07/05 AT49BV6416C(T) 25. Ordering Information 25.1 tACC (ns) 70 70 Standard Packaging ICC (mA) Active 30 30 Standby 0.035 0.035 Ordering Code AT49BV6416C-70CI AT49BV6416CT-70CI Package 48C20 48C20 Operation Range Industrial (-40 to 85C) Industrial (-40 to 85C) Package Type 48C20 48-ball, Plastic Chip-size Ball Grid Array Package (CBGA) 29 3465C-FLASH-07/05 26. Packaging Information 26.1 48C20 - CBGA E A1 BALL ID D Top View A1 0.875 REF E1 e A A1 BALL CORNER 3.125 REF Side View COMMON DIMENSIONS (Unit of Measure = mm) A B SYMBOL E MIN 6.90 NOM 7.00 5.25 TYP MAX 7.10 NOTE C D E F D1 E1 D D1 A A1 e - 0.21 9.90 10.00 3.75 TYP - - 0.75 BSC 0.35 TYP 10.10 1.0 - 8 7 Ob 6 5 4 3 2 1 Ob Bottom View 01/8/04 2325 Orchard Parkway San Jose, CA 95131 TITLE 48C20, 48-ball (8 x 6 Array),0.75 mm Pitch, 7.0 x 10.0 x 1.0 mm Chip-scale Ball Grid Array Package (CBGA) DRAWING NO. 48C20 REV. A R 30 AT49BV6416C(T) 3465C-FLASH-07/05 AT49BV6416C(T) 27. Revision History Revision No. Revision A - April 2004 History * * * * * * * Initial Release Removed "Preliminary" from the datasheet. Modified note 6 and added notes 7 and 10 on page 13. Modified note 1 and added note 2 on page 14. Changed the ISB1 spec to 35 A. Converted datasheet to new template. Changed the VPP value to 9.5 0.5V in the text, tables on pages 15, 16, 21 and CFI table on page 27. VPP text also changed to show that a high voltage on VPP improves only the programming time. Changed the maximum voltage that can be applied on the address inputs and control inputs to 5.5V on page 9. Changed the maximum input voltage under absolute maximum ratings to 6.25V on page 16. Revision B - November 2004 Revision C - July 2005 * * 31 3465C-FLASH-07/05 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life (c) Atmel Corporation 2005. All rights reserved. Atmel(R), logo and combinations thereof, Everywhere You Are (R) and others, are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Printed on recycled paper. 3465C-FLASH-07/05 |
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